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36-mbit qdr?-ii sram 2-word burst architecture cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-12561 rev. *f revised july 31, 2009 features separate independent read and write data ports ? supports concurrent transactions 267 mhz clock for high bandwidth 2-word burst on all accesses double data rate (ddr) interfaces on both read and write ports (data transferred at 534 mhz) at 267 mhz two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only two input clocks for output data (c and c ) to minimize clock skew and flight time mismatches echo clocks (cq and cq ) simplify data capture in high speed systems single multiplexed address i nput bus latches address inputs for both read and write ports separate port select s for depth expansion synchronous internally self-timed writes qdr?-ii operates with 1.5 cycle read latency when delay lock loop (dll) is enabled operates like a qdr-i device with 1 cycle read latency in dll off mode available in x8, x9, x18, and x36 configurations full data coherency, providing most current data core v dd = 1.8v (0.1v); i/o v ddq = 1.4v to v dd available in 165-ball fbga package (15 x 17 x 1.4 mm) offered in both pb-free and non pb-free packages variable drive hstl output buffers jtag 1149.1 compatib le test access port delay lock loop (dll) for a ccurate data placement configurations cy7c1410jv18 ? 4m x 8 CY7C1425JV18 ? 4m x 9 cy7c1412jv18 ? 2m x 18 cy7c1414jv18 ? 1m x 36 functional description the cy7c1410jv18, CY7C1425JV18, cy7c1412jv18, and cy7c1414jv18 are 1.8v synchronous pipelined srams, equipped with qdr-ii architecture. qdr-ii architecture consists of two separate ports: the read port and the write port, to access the memory array. the read port has data outputs to support read operations and the write port has data inputs to support write operations. qdr-ii architecture has separate data inputs and data outputs to eliminate the need to ?turnaround? the data bus required with common i/o devices. access to each port is accomplished through a common address bus. the read address is latched on the rising edge of the k clock and the write address is latched on the rising edge of the k clock. accesses to the qdr-ii read and write ports are completely independent of one another. to maximize data throughput, both read and write ports are provided with ddr interfaces. each address location is associated with two 8-bit wo rds (cy7c1410jv18), 9-bit words (CY7C1425JV18), 18-bit words (cy7c1412jv18), or 36-bit words (cy7c1414jv18) that burst sequentially into or out of the device. because data is transferred into and out of the device on every rising edge of both input clocks (k and k and c and c ), memory bandwidth is maximized while simplifying system design by eliminating bus ?turnarounds?. depth expansion is accomplished with port selects, which enables each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c (or k or k in a single clock domain) input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. selection guide description 267 mhz 250 mhz unit maximum operating frequency 267 250 mhz maximum operating current x8 1330 1200 ma x9 1330 1200 x18 1370 1230 x36 1460 1290 [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 2 of 26 logic block diagram (cy7c1410jv18) logic block diagram (CY7C1425JV18) 2m x 8 array clk a (20:0) gen. k k control logic address register d [7:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 8 21 16 8 nws [1:0] v ref write add. decode write reg 8 a (20:0) 21 cq cq doff q [7:0] 8 8 8 write reg c c 2m x 8 array 2m x 9 array clk a (20:0) gen. k k control logic address register d [8:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 9 21 18 9 bws [0] v ref write add. decode write reg 9 a (20:0) 21 cq cq doff q [8:0] 9 9 9 write reg c c 2m x 9 array [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 3 of 26 logic block diagram (cy7c1412jv18) logic block diagram (cy7c1414jv18) 1m x 18 array clk a (19:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 18 20 36 18 bws [1:0] v ref write add. decode write reg 18 a (19:0) 20 cq cq doff q [17:0] 18 18 18 write reg c c 1m x 18 array 512k x 36 array clk a (18:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 36 19 72 36 bws [3:0] v ref write add. decode write reg 36 a (18:0) 19 cq cq doff q [35:0] 36 36 36 write reg c c 512k x 36 array [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 4 of 26 pin configuration the pin configuration for cy7c1410jv18, cy7c1412jv18, and cy7c1414jv18 follow. [1] 165-ball fbga (15 x 17 x 1.4 mm) pinout cy7c1410jv18 (4m x 8) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/72m a wps nws 1 k nc/144m rps aacq b nc nc nc a nc/288m k nws 0 ancncq3 c nc nc nc v ss aaav ss nc nc d3 d nc d4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q4 v ddq v ss v ss v ss v ddq nc d2 q2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d5 q5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q1 d1 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q6 d6 v ddq v ss v ss v ss v ddq nc nc q0 m nc nc nc v ss v ss v ss v ss v ss nc nc d0 n nc d7 nc v ss aaav ss nc nc nc p nc nc q7 a a c a a nc nc nc r tdo tck a a a c aaatmstdi CY7C1425JV18 (4m x 9) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/72m a wps nc k nc/144m rps aacq b nc nc nc a nc/288m k bws 0 ancncq4 c nc nc nc v ss aaav ss nc nc d4 d nc d5 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q5 v ddq v ss v ss v ss v ddq nc d3 q3 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d6 q6 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q2 d2 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q7 d7 v ddq v ss v ss v ss v ddq nc nc q1 m nc nc nc v ss v ss v ss v ss v ss nc nc d1 n nc d8 nc v ss aaav ss nc nc nc p nc nc q8 a a c a a nc d0 q0 r tdo tck a a a c aaatmstdi note 1. nc/72m, nc/144m and nc/288m are not connected to the die and can be tied to any voltage level. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 5 of 26 cy7c1412jv18 (2m x 18) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/144m a wps bws 1 k nc/288m rps a nc/72m cq b nc q9 d9 a nc k bws 0 ancncq8 c nc nc d10 v ss aaav ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss aaav ss nc nc d1 p nc nc q17 a a c a a nc d0 q0 r tdo tck a a a c aaatmstdi cy7c1414jv18 (1m x 36) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/288m nc/72m wps bws 2 k bws 1 rps a nc/144m cq b q27 q18 d18 a bws 3 kbws 0 ad17q17q8 c d27 q28 d19 v ss aaav ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss aaav ss q10 d9 d1 p q35 d35 q26 a a c a a q9 d0 q0 r tdo tck a a a c aaatmstdi pin configuration the pin configuration for cy7c1410jv18, cy7c1412jv18, and cy7c1414jv18 follow. [1] (continued) 165-ball fbga (15 x 17 x 1.4 mm) pinout [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 6 of 26 pin definitions pin name i/o pin description d [x:0] input- synchronous data input signals. sampled on the rising edge of k and k clocks during valid write operations. cy7c1410jv18 - d [7:0] CY7C1425JV18 - d [8:0] cy7c1412jv18 - d [17:0] cy7c1414jv18 - d [35:0] wps input- synchronous write port select ? active low . sampled on the rising edge of the k clock. when asserted active, a write operation is initiated. dea sserting deselects the write port. deselecting the write port ignores d [x:0] . nws 0 , nws 1 nibble write select 0, 1 ? active low (cy7c1410jv18 only) . sampled on the rising edge of the k and k clocks during write operations. used to select which nibble is written into the device during the current portion of the write operations.n ibbles not written remain unaltered. nws 0 controls d [3:0] and nws 1 controls d [7:4] . all nibble write selects are sampled on the same e dge as the data. deselecting a nibble write select ignores the corresponding nibble of data and it is not written into the device. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of the k and k clocks during write operations. used to select which byte is written int o the device during the current portion of the write operations. bytes not written remain unaltered. CY7C1425JV18 ? bws 0 controls d [8:0] cy7c1412jv18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] . cy7c1414jv18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] ,bws 2 controls d [26:18] and bws 3 controls d [35:27]. all the byte write selects are sampled on the same edge as the data. deselecting a byte write select ignores the corresponding byte of data and it is not written into the device. a input- synchronous address inputs. sampled on the rising edge of the k (read address) and k (write address) clocks during active read and write operations. these address inputs are multiplexed for both read and write operations. internally, the device is organized as 4m x 8 (2 a rrays each of 2m x 8) for cy7c1410jv18, 4m x 9 (2 arrays each of 2m x 9) for CY7C1425JV18, 2m x 18 (2 arrays each of 1m x 18) for cy7c1412jv18 and 1m x 36 (2 arrays each of 512k x 36) for cy7c141 4jv18. therefore, only 21 address inputs are needed to access the entire memory array of cy7c1410jv18 and CY7C1425JV18, 20 address inputs for cy7c1412jv18 and 19 address inputs for cy7c1414jv1 8. these inputs are ignored when the appro- priate port is deselected. q [x:0] outputs- synchronous data output signals . these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations, or k and k when in single clock mode. when the read port is deselected, q [x:0] are automatically tri-stated. cy7c1410jv18 ? q [7:0] CY7C1425JV18 ? q [8:0] cy7c1412jv18 ? q [17:0] cy7c1414jv18 ? q [35:0] rps input- synchronous read port select ? active low . sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasse rting deselects the read port. when deselected, the pending access is enabled to complete and the output drivers are automati cally tri-stated following the next rising edge of the c clock. each read access consists of a burst of two sequential transfers. c input clock positive input clock for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight ti mes of various devices on the board back to the controller. see application example on page 9 for further details. c input clock negative input clock for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight ti mes of various devices on the board back to the controller. see application example on page 9 for further details. k input clock positive input clock input . the rising edge of k is used to c apture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all acce sses are initiated on the rising edge of k. k input clock negative input clock input . k is used to capture synchronous input s being presented to the device and to drive out data through q [x:0] when in single clock mode. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 7 of 26 cq echo clock cq is referenced with respect to c . this is a free-running clock and is synchronized to the input clock for output data (c) of the qdr-ii. in the single clock mode, cq is generated with respect to k. the timings for the echo clocks is shown in the switching characteristics on page 22. cq echo clock cq is referenced with respect to c . this is a free-running clock and is synchronized to the input clock for output data (c ) of the qdr-ii. in the single clock mode, cq is generated with respect to k . the timings for the echo clocks is shown in the switching characteristics on page 22. zq input output impedance matching input . this input is used to tune the dev ice outputs to the system data bus impedance. cq, cq , and q [x:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternatively, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. doff input dll turn off ? active low . connecting this pin to ground turns off the dll inside the device. the timing in the dll turned off operation differs from those li sted in this data sheet. for normal operation, this pin is connected to a pull up through a 10-kohm or le ss pull up resistor. the device behaves in ddr-i mode when the dll is turned off. in this mode, the devic e operates at a frequency of up to 167 mhz with qdr-i timing. tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc n/a not connected to the die . can be tied to any voltage level. nc/72m n/a not connected to the die . can be tied to any voltage level. nc/144m n/a not connected to the die . can be tied to any voltage level. nc/288m n/a not connected to the die . can be tied to any voltage level. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs, outputs, and ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name i/o pin description [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 8 of 26 functional overview the cy7c1410jv18, cy7c142 5jv18, cy7c1412jv18, and cy7c1414jv18 are synchronous pipelined burst srams with a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and flows out through the read port. these devices multiplex the address inputs to minimize the number of address pins required. by having separate read and write ports, the qdr-ii eliminates the need to ?turnaround? the data bus and avoids any possible data contention, thereby simplifyi ng system design. each access consists of two 8-bit data transfers in the case of cy7c1410jv18, two 9-bit data transfers in the case of CY7C1425JV18, two 18-bit data transfers in the case of cy7c1412jv18, and two 36-bit data transfers in the case of cy7c1414jv18 in one clock cycle. this device operates with a read latency of one and half cycles when doff pin is tied high. when doff pin is set low or connected to v ss, the device behaves in qdr-i mode with a read latency of one clock cycle. accesses for both ports are initiated on the rising edge of the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the rising edge of the output clocks (c and c, or k and k when in single clock mode). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the input clocks (k and k ). all synchronous data outputs (q [x:0] ) pass through output registers controlled by the rising edge of the ou tput clocks (c and c, or k and k when in single clock mode). all synchronous control (rps , wps , bws [x:0] ) inputs pass through input registers controlled by the rising edge of the input clocks (k and k ). cy7c1412jv18 is described in the following sections. the same basic descriptions apply to cy7c1410jv18, CY7C1425JV18, and cy7c1414jv18. read operations the cy7c1412jv18 is organized internally as two arrays of 1m x 18. accesses are completed in a burst of two sequential 18-bit data words. read operations are initiated by asserting rps active at the rising edge of th e positive input clock (k). the address is latched on the rising edge of the k clock. the address presented to the address inputs is stored in the read address register. following the next k clock rise, the corresponding lowest order 18-bit word of data is driven onto the q [17:0] using c as the output timing reference. on the subsequent rising edge of c, the next 18-bit data word is driven onto the q [17:0] . the requested data is valid 0.45 ns fr om the rising edge of the output clock (c and c or k and k when in single clock mode). synchronous internal circuitry aut omatically tri-states the outputs following the next rising edge of the output clocks (c/c ). this enables a seamless transition between devices without the insertion of wait states in a depth expanded memory. write operations write operations are init iated by asserting wps active at the rising edge of the positive input clock (k). on the same k clock rise, the data presented to d [17:0] is latched and stored into the lower 18-bit write data register, provided bws [1:0] are both asserted active. on the subseque nt rising edge of the negative input clock (k ), the address is latched and the information presented to d [17:0] is stored into the write data register, provided bws [1:0] are both asserted active. the 36 bits of data are then written into the memory array at the specified location. when deselected, the write port ignores all inputs after completion of pending write operations. byte write operations byte write operations are s upported by the cy7c1412jv18. a write operation is initi ated as described in the write operations section. the bytes that are wr itten are determined by bws 0 and bws 1 , which are sampled with each 18-bit data word. asserting the byte write select input during the data portion of a write latches the data being presented a nd writes it into the device. deasserting the byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. this feature is used to simplify, read, modify, or write operations to a byte write operation. single clock mode the cy7c1412jv18 is used with a single clock that controls both the input and output regist ers. in this mode, the device recognizes only a single pair of input clocks (k and k ) that control both the input and output registers . this operation is identical to the operation if the device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, tie c and c high at power on. this function is a strap option and not alterable during device operation. concurrent transactions the read and write ports on the cy7c1412jv18 operate independently of one another. as each port latches the address inputs on different clock edges, th e user reads or writes to any location, regardless of the tran saction on the other port. the user can start reads and writes in the same clock cycle. if the ports access the same location at the same time, the sram delivers the most recent information associated with the specified address location. this includes forwarding data from a write cycle that was initiated on the previous k clock rise. depth expansion the cy7c1412jv18 has a port select input for each port. this enables easy depth expansion. both port selects are sampled on the rising edge of the positive input clock only (k). each port select input deselects the specified port. deselecting a port does not affect the other port. all pending transactions (read and write) are completed prior to the device being deselected. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 9 of 26 programmable impedance an external resistor, rq, is connected between the zq pin on the sram and v ss to enable the sram to adjust its output driver impedance. the value of rq is five times the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a tolerance of 15 percent is between 175 and 350 , with v ddq =1.5v. the output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on the qd r-ii to simplify data capture on high speed systems. two echo clocks are generated by the qdr-ii. cq is referenced with respect to c and cq is referenced with respect to c . these are free-running clocks and are synchronized to the output clock (c/c ) of the qdr-ii. in single clock mode, cq is generated with respect to k and cq is generated with respect to k . the timing for the echo clocks is shown in the switching characteristics on page 22. dll these chips utilize a delay lock loop (dll) that is designed to function between 120 mhz and the specified maximum clock frequency. during power up, when the doff is tied high, the dll is locked after 1024 cycles of stable clock. the dll is also reset by slowing or stopping the input clock k and k for a minimum of 30 ns. however, it is not necessary to reset the dll to lock to the desired frequency. the dll automatically locks 1024 clock cycles after a stable clock is presented. disable the dll by applying ground to the doff pin. when the dll is turned off, the device behaves in qdr-i mode (with one cycle latency and a longer access time). for information refer to the application note dll considerations in qdrii/ddrii. application example figure 1 shows two qdr-ii used in an application. figure 1. application example r = 250 ohms vt r r = 250 ohms vt vt r vt = vddq/2 r = 50 ohms r cc# d a sram #2 r p s # w p s # b w s # zq cq/cq# q k# cc# d a k sram #1 r p s # w p s # b w s # zq cq/cq# q k# bus master (cpu or asic) data in data out address rps# wps# bws# source k source k# delayed k delayed k# clkin/clkin# k [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 10 of 26 truth table the truth table for cy7c1410jv18, CY7C1425JV18 , cy7c1412jv18, and cy7c1414jv18 follows. [2, 3, 4, 5, 6, 7] operation k rps wps dq dq write cycle: load address on the rising edge of k ; input write data on k and k rising edges. l-h x l d(a + 0) at k(t) d(a + 1) at k (t) read cycle: load address on the rising edge of k; wait one and a half cycle; read data on c and c rising edges. l-h l x q(a + 0) at c (t + 1) q(a + 1) at c(t + 2) nop: no operation l-h h h d = x q = high-z d = x q = high-z standby: clock stopped stopped x x previous state previous state write cycle descriptions the write cycle description table for cy7c1410jv18 and cy7c1412jv18 follows. [2, 8] bws 0 / nws 0 bws 1 / nws 1 k k comments l l l?h ? during the data portion of a write sequence : cy7c1410jv18 ? both nibbles (d [7:0] ) are written into the device. cy7c1412jv18 ? both bytes (d [17:0] ) are written into the device. l l ? l-h during the data portion of a write sequence : cy7c1410jv18 ? both nibbles (d [7:0] ) are written into the device. cy7c1412jv18 ? both bytes (d [17:0] ) are written into the device. l h l?h ? during the data portion of a write sequence : cy7c1410jv18 ? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c1412jv18 ? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. l h ? l?h during the data portion of a write sequence : cy7c1410jv18 ? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c1412jv18 ? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. h l l?h ? during the data portion of a write sequence : cy7c1410jv18 ? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c1412jv18 ? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h l ? l?h during the data portion of a write sequence : cy7c1410jv18 ? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c1412jv18 ? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h h l?h ? no data is written into the devices during this portion of a write operation. h h ? l?h no data is written into the devices during this portion of a write operation. notes 2. x = ?don't care,? h = logic high, l = logic low, represents rising edge. 3. device powers up deselected with the outputs in a tri-state condition. 4. ?a? represents address location latched by the devices when tr ansaction was initiated. a + 0, a + 1 represents the internal a ddress sequence in the burst. 5. ?t? represents the cycle at which a read/write operation is st arted. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 7. it is recommended that k = k and c = c = high when clock is stopped. this is not essential, but per mits most rapid restart by overcoming transmission line charging symmetrically. 8. is based on a write cycle that was initiated in accordance with the write cycle descriptions table. nws 0 , nws 1, bws 0 , bws 1, bws 2 and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 11 of 26 write cycle descriptions the write cycle description tabl e for CY7C1425JV18 follows. [2, 8] bws 0 k k comments l l?h ? during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. l ? l?h during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. h l?h ? no data is written into the device du ring this portion of a write operation. h ? l?h no data is written into the device du ring this portion of a write operation. write cycle descriptions the write cycle description tabl e for cy7c1414jv18 follows. [2, 8] bws 0 bws 1 bws 2 bws 3 k k comments lllll?h?dur ing the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. llll?l?hdur ing the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l?h ? during the data portion of a writ e sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h ? l?h during the data portion of a writ e sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h l?h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h ? l?h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h l?h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h ? l?h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l l?h ? during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l ? l?h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. hhhhl?h?no data is written into the device during this portion of a write operation. hhhh?l?hno data is written into the device during this portion of a write operation. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 12 of 26 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard 1149.1-2001. the tap operates using jedec standard 1.8v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tie tck low (v ss ) to prevent clocking of the device. td i and tms are internally pulled up and are unconnected. they ma y alternatively be connected to v dd through a pull up resistor. leave tdo unconnected. upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. leave this pin uncon- nected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram on page 14. tdi is internally pulled up and is uncon- nected if the tap is unused in an application. tdi is connected to the most significant bi t (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is active, depending upon the current state of the tap state machine (see instruction codes on page 17). the output changes on the falling edge of tck. tdo is connected to the least signific ant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and is performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins to scan the data in and out of the sram test circuitry. select only one register at a time through the inst ruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions are seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins, as shown in tap controller block diagram on page 15. upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state, as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to enable fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, skip certain chips. the bypass register is a single-bit register that is placed between tdi and tdo pins. this enables shifting of data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is l oaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload, and sample z instructions can be used to capture the contents of the input and output ring. the boundary scan order on page 18 shows the order in which the bits are connected. each bi t corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and is shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other infor- mation described in identification register definitions on page 17. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in instruction codes on page 17. do not use thr ee of these instructions that are listed as reserved. the ot her five instructions are described in this section in detail. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instruc tions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction after it is shifted in, move the tap controller into the update-ir state. idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction register. it also places the instruction register [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 13 of 26 between the tdi and tdo pins and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded in to the instruction register at power up or whenever the tap controller is given a test-logic-reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the nex t command is given during the update ir state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the input and output pins is captured in the boundary scan register. the tap controller clock only operates at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a tr ansition. the tap then tries to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, stabilize the sram signal long enough to meet the tap controller's capture setup plus hold times (t cs and t ch ). the sram clock input m ight not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if th is is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. the shifting of data for the sample and preload phases occurs concurrently when required, that is, while the data captured is shifted out, the preloaded data is shifted in. bypass when the bypass instructio n is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction drives the preloaded data out through the system output pi ns. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates t hat the tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit 108. when this scan cell, called the ?e xtest output bus tri-state?, is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high-z condition. this bit is set by enteri ng the sample/preload or extest command, and then shifting the de sired bit into that cell, during the shift-dr state. during upda te-dr, the value loaded into that shift-register cell latches into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is preset low to enable the output when the device is powered up, and also when the tap controller is in the test-logic-reset state. reserved these instructions are not implemented but are reserved for future use. do not use these instructions. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 14 of 26 tap controller state diagram the state diagram for the tap controller follows. [9] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir note 9. the 0/1 next to each state represents the value at tms at the rising edge of tck. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 15 of 26 tap controller block diagram tap electrical characteristics over the operating range [10, 11, 12] parameter description test conditions min max unit v oh1 output high voltage i oh = ? 2.0 ma 1.4 v v oh2 output high voltage i oh = ? 100 a1.6 v v ol1 output low voltage i ol = 2.0 ma 0.4 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 0.65v dd v dd + 0.3 v v il input low voltage ?0.3 0.35v dd v i x input and output load current gnd v i v dd ?5 5 a 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 108 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms notes 10. these characteristics pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics table. 11. overshoot: v ih (ac) < v ddq + 0.85v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 1.5v (pulse width less than t cyc /2). 12. all voltage referenced to ground. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 16 of 26 tap ac switching characteristics over the operating range [13, 14] parameter description min max unit t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high 20 ns t tl tck clock low 20 ns setup times t tmss tms setup to tck clock rise 5 ns t tdis tdi setup to tck clock rise 5 ns t cs capture setup to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns tap timing and test conditions figure 2 shows the tap timing and test conditions. [14] figure 2. tap timing and test conditions t tl t th (a) tdo c l = 20 pf z 0 = 50 gnd 0.9v 50 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data in tdi test data out t tcyc t tmsh t tmss t tdis t tdih t tdov t tdox tdo notes 13. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 14. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 17 of 26 identification register definitions instruction field value description cy7c1410jv18 CY7C1425JV18 cy7c1412jv18 cy7c1414jv18 revision number (31:29) 000 000 000 000 version number. cypress device id (28:12) 11010011010000111 11010011010001111 11010011010010111 11010011010100111 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1111indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 109 instruction codes instruction code description extest 000 captures the input and output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input and output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input and output ring c ontents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 18 of 26 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 28 10g 56 6a 84 1j 16p299g575b852j 2 6n 30 11f 58 5a 86 3k 3 7p 31 11g 59 4a 87 3j 47n329f605c882k 5 7r 33 10f 61 4b 89 1k 6 8r 34 11e 62 3a 90 2l 7 8p 35 10e 63 2a 91 3l 8 9r 36 10d 64 1a 92 1m 9 11p 37 9e 65 2b 93 1l 10 10p 38 10c 66 3b 94 3n 11 10n 39 11d 67 1c 95 3m 12 9p 40 9c 68 1b 96 1n 13 10m 41 9d 69 3d 97 2m 14 11n 42 11b 70 3c 98 3p 15 9m 43 11c 71 1d 99 2n 16 9n 44 9b 72 2c 100 2p 17 11l 45 10b 73 3e 101 1p 18 11m 46 11a 74 2d 102 3r 19 9l 47 10a 75 2e 103 4r 20 10l 48 9a 76 1e 104 4p 21 11k 49 8b 77 2f 105 5p 22 10k 50 7c 78 3f 106 5n 23 9j 51 6c 79 1g 107 5r 24 9k 52 8a 80 1f 108 internal 25 10j 53 7a 81 3g 26 11j 54 7b 82 2g 27 11h 55 6b 83 1h [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 19 of 26 power up sequence in qdr-ii sram power up and initialize qdr-ii srams in a predefined manner to prevent undefined operations. power up sequence apply power and drive doff either high or low (all other inputs can be high or low). ? apply v dd before v ddq . ? apply v ddq before v ref or at the same time as v ref . ? drive doff high. provide stable doff (high), power and clock (k, k ) for 1024 cycles to lock the dll. dll constraints dll uses k clock as its synchr onizing input. the input has low phase jitter, which is specified as t kc var . the dll functions at frequencies down to 120 mhz. if the input clock is unstable and the dll is enabled, then the dll may lock onto an incorrect frequency, causing unstable sram behavior. to avoid this, provide1024 cycles stable clock to relock to the desired clock frequency. figure 3. power up waveforms > 1024 stable clock start normal operation doff stabl e (< +/- 0.1v dc per 50ns ) fix high (or tie to v ddq ) k k ddq dd v v / ddq dd v v / clock start ( clock starts after stable ) ddq dd v v / ~ ~ ~ ~ unstable clock [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 20 of 26 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65c to +150c ambient temperature with power applied.. ?55c to +125c supply voltage on v dd relative to gnd ........?0.5v to +2.9v supply voltage on v ddq relative to gnd.......?0.5v to +v dd dc applied to outputs in high-z ........ ?0.5v to v ddq + 0.3v dc input voltage [11] .............................. ?0.5v to v dd + 0.3v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, m. 3015).. > 2001v latch-up current ................................................... > 200 ma operating range range ambient temperature (t a ) v dd [15] v ddq [15] commercial 0c to +70c 1.8 0.1v 1.4v to v dd industrial ?40c to +85c electrical characteristics dc electrical characteristics over the operating range [12] parameter description test conditions min typ max unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 v dd v v oh output high voltage note 16 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v ol output low voltage note 17 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ? 0.1 ma, nominal impedance v ddq ? 0.2 v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss 0.2 v v ih input high voltage v ref + 0.1 v ddq + 0.3 v v il input low voltage ?0.3 v ref ? 0.1 v i x input leakage current gnd v i v ddq ? 5 5 a i oz output leakage current gnd v i v ddq, output disabled ? 5 5 a v ref input reference voltage [18] typical value = 0.75v 0.68 0.75 0.95 v i dd [19] v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 267 mhz (x8) 1330 ma (x9) 1330 (x18) 1370 (x36) 1460 250 mhz (x8) 1200 ma (x9) 1200 (x18) 1230 (x36) 1290 i sb1 automatic power down current max v dd , both ports deselected, v in v ih or v in v il f = f max = 1/t cyc , inputs static 267 mhz (x8) 375 ma (x9) 375 (x18) 380 (x36) 385 250 mhz (x8) 345 ma (x9) 345 (x18) 350 (x36) 350 notes 15. power up: assumes a linear ramp from 0v to v dd (min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 16. output are impedance controlled. i oh = ? (v ddq /2)/(rq/5) for values of 175 ohms <= rq <= 350 ohms. 17. output are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ohms <= rq <= 350 ohms. 18. v ref (min) = 0.68v or 0.46v ddq , whichever is larger, v ref (max) = 0.95v or 0.54v ddq , whichever is smaller. 19. the operation current is calculated with 50% read cycle and 50% write cycle. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 21 of 26 ac electrical characteristics over the operating range [11] parameter description test conditions min typ max unit v ih input high voltage v ref + 0.2 ? ? v v il input low voltage ? ? v ref ? 0.2 v capacitance tested initially and after any design or process change that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 1.8v, v ddq = 1.5v 5 pf c clk clock input capacitance 4 pf c o output capacitance 5pf thermal resistance tested initially and after any design or process change that may affect these parameters. parameter description test conditions 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 17.2 c/w jc thermal resistance (junction to case) 3.2 c/w figure 4. ac test loads and waveforms 1.25v 0.25v r = 50 5pf including jig and scope all input pulses device r l = 50 z 0 = 50 v ref = 0.75v v ref = 0.75v [20] 0.75v under te s t 0.75v device under te s t output 0.75v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 (b) rq = 250 20. unless otherwise noted, test conditions are based on signal tr ansition time of 2v/ns, timing reference levels of 0.75v, vref = 0.75v, rq = 250 , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads and waveforms . [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 22 of 26 switching characteristics over the operating range [20, 21] cypress parameter consortium parameter description 267 mhz 250 mhz unit min max min max t power v dd (typical) to the first access [22] 11ms t cyc t khkh k clock and c clock cycle time 3.75 8.4 4.0 8.4 ns t kh t khkl input clock (k/k and c/c ) high 1.5?1.6? ns t kl t klkh input clock (k/k and c/c ) low 1.5 ? 1.6 ? ns t khk h t khk h k clock rise to k clock rise and c to c rise (rising edge to rising edge) 1.68 ? 1.8 ? ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0 1.68 0 1.8 ns setup times t sa t avkh address setup to k cl ock rise 0.3 ? 0.35 ? ns t sc t ivkh control setup to k clock rise (rps , wps ) 0.3 ?0.35? ns t scddr t ivkh ddr control set up to clock (k/k ) rise (bws 0 , bws 1 , bws 3 , bws 4 ) 0.3 ?0.35? ns t sd t dvkh d [x:0] setup to clock (k/k ) rise 0.3 ? 0.35 ? ns hold times t ha t khax address hold after k clock rise 0.3 ? 0.35 ? ns t hc t khix control hold after k clock rise (rps , wps ) 0.3 ?0.35? ns t hcddr t khix ddr control hold after clock (k/k ) rise (bws 0 , bws 1 , bws 3 ,bws 4 ) 0.3 ?0.35? ns t hd t khdx d [x:0] hold after clock (k/k ) rise 0.3 ? 0.35 ? ns output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid ? 0.45 ? 0.45 ns t doh t chqx data output hold after output c/c clock rise (active to active) ?0.45 ? ?0.45 ? ns t ccqo t chcqv c/c clock rise to echo clock valid ? 0.45 ? 0.45 ns t cqoh t chcqx echo clock hold after c/c clock rise ?0.45 ? ?0.45 ? ns t cqd t cqhqv echo clock high to data valid ? 0.27 ? 0.30 ns t cqdoh t cqhqx echo clock high to data invalid ?0.27 ? ?0.30 ? ns t cqh t cqhcql output clock (cq/cq ) high [23] 1.43 ? 1.55 ? ns t cqhcq h t cqhcq h cq clock rise to cq clock rise (rising edge to rising edge) [23] 1.43 ? 1.55 ? ns t chz t chqz clock (c/c ) rise to high-z (active to high-z) [24, 25] ?0.45?0.45ns t clz t chqx1 clock (c/c ) rise to low-z [24, 25] ?0.45 ? ?0.45 ? ns dll timing t kc var t kc var clock phase jitter ? 0.20 ? 0.20 ns t kc lock t kc lock dll lock time (k, c) 1024 ? 1024 ? cycles t kc reset t kc reset k static to dll reset 30 ? 30 ? ns notes 21. when a part with a maximum frequency above 250 mhz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 22. this part has a voltage regulator internally; t power is the time that the power is supplied above v dd minimum initially before a read or write operation can be initiated. 23. these parameters are extrapolated from the input timing parameters (t khkh - 250 ps, where 250 ps is the internal jitter. an input jitter of 200 ps (t kc var) is already included in the t khkh ). these parameters are only guaranteed by design and are not tested in production. 24. t chz , t clz , are specified with a load capacit ance of 5 pf as in part (b) of ac test loads and waveforms on page 21. transition is measured 100 mv from steady state voltage. 25. at any voltage and temperature t chz is less than t clz and t chz less than t co . [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 23 of 26 switching waveforms figure 5. read/write/deselect sequence [26, 27, 28] k 1 2 34 5 8 10 6 7 k rps wps a d read read write write write nop read write nop 9 a0 t kh t khkh t kl t cyc tt hc t sa t ha t sd t hd sc t t sa t ha t sd t hd a6 a5 a3 a4 a1 a2 d30 d50 d51 d61 d31 d11 d10 d60 q c c dont care undefined t cq cq t khch t co t khch t clz chz t kh t kl q00 q01 q20 t khkh t cyc q21 q40 q41 t cqd t doh t ccqo t cqoh t ccqo t cqoh t cqdoh t cqh t cqhcqh notes 26. q00 refers to output from address a0. q01 refers to output fr om the next internal burst address following a0, that is, a0+1. 27. outputs are disabled (high-z) one clock cycle after a nop. 28. in this example, if address a2 = a1, then data q20 = d10 and q21 = d11. write data is forwarded immediately as read results. this note applies to the whole diagram. [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 24 of 26 ordering information not all of the speed, package and temperature ranges are avai lable. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range 267 cy7c1410jv18-267bzc 51-85195 165-ball fine pitc h ball grid array (15 x 17 x 1.4 mm) commercial CY7C1425JV18-267bzc cy7c1412jv18-267bzc cy7c1414jv18-267bzc cy7c1410jv18-267bzxc 51-85195 165-b all fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free CY7C1425JV18-267bzxc cy7c1412jv18-267bzxc cy7c1414jv18-267bzxc cy7c1410jv18-267bzi 51-85195 165-b all fine pitch ball grid array (15 x 17 x 1.4 mm) industrial CY7C1425JV18-267bzi cy7c1412jv18-267bzi cy7c1414jv18-267bzi cy7c1410jv18-267bzxi 51-85195 165-b all fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free CY7C1425JV18-267bzxi cy7c1412jv18-267bzxi cy7c1414jv18-267bzxi 250 cy7c1410jv18-250bzc 51-85195 165-ball fine pitc h ball grid array (15 x 17 x 1.4 mm) commercial CY7C1425JV18-250bzc cy7c1412jv18-250bzc cy7c1414jv18-250bzc cy7c1410jv18-250bzxc 51-85195 165-b all fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free CY7C1425JV18-250bzxc cy7c1412jv18-250bzxc cy7c1414jv18-250bzxc cy7c1410jv18-250bzi 51-85195 165-b all fine pitch ball grid array (15 x 17 x 1.4 mm) industrial CY7C1425JV18-250bzi cy7c1412jv18-250bzi cy7c1414jv18-250bzi cy7c1410jv18-250bzxi 51-85195 165-b all fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free CY7C1425JV18-250bzxi cy7c1412jv18-250bzxi cy7c1414jv18-250bzxi [+] feedback
cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 document #: 001-12561 rev. *f page 25 of 26 package diagram figure 6. 165-ball fbga (15 x 17 x 1.40 mm), 51-85195 a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.50 (165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.350.06 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.14 -0.06 solder pad type : non solder mask defined (nsmd) notes : package weight : 0.65g jedec reference : mo-216 / design 4.6c package code : bb0ad 51-85195-*a [+] feedback
document #: 001-12561 rev. *f revised july 31, 2009 page 26 of 26 qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all pr oduct and company names mentioned in this document are the trademarks of their respective holders. cy7c1410jv18, CY7C1425JV18 cy7c1412jv18, cy7c1414jv18 ? cypress semiconductor corporation, 2007-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems applic ation implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com document history page document title: cy7c1410jv18/cy 7c1425jv18/cy7c1412jv18/cy7c1414jv 18, 36-mbit qdr?-ii sram 2-word burst architecture document number: 001-12561 rev. ecn orig. of change submission date description of change ** 808457 vkn see ecn new data sheet *a 1061960 vkn see ecn removed 300mhz speed bin *b 1397384 vkn see ecn added 267mhz speed bin *c 1462587 vkn/aesa see ecn converted from preliminary to final removed 200mhz speed bin updated i dd /i sb specs changed dll minimum operating frequency from 80mhz to 120mhz changed t cyc max spec to 8.4ns for all speed bins *d 2189567 vkn/aesa see ecn minor change-moved to the external web *e 2561954 vkn/pyrs 09/04/08 changed ambient temperature with power applied from ??10c to +85c? to ??55c to +125 c? in the ?maximum ratings ? on page 20, updated power-up sequence waveform and it?s description, added footnote #19 related to i dd , changed jtag id [31:29] from 001 to 000. *f 2746930 07/31/09 njy post to external website [+] feedback

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